1. Field of the Invention
The present invention relates to electronic switches. In particular, the present invention relates to semiconductor switches, including those formed of one or more metal-oxide-semiconductor (MOS) transistors. More particularly, the present invention relates to analog and digital semiconductor switches, including but not limited to, those defined as pass-gate transistors or transfer gates.
2. Description of the Prior Art
Developments in semiconductor technology have created the capability to produce low-cost, highly reliable switches that are, effectively, implementations of mechanical relays. They have been found to be of particular use, when implemented, as single pole, single throw, type relays, but are not limited thereto. Semiconductor switches are being used more and more as replacements for the prior mechanical relays, due to the high switching speed available as well as their ability to transfer relatively high currents without failure. These switches are often referred to as transfer gates or pass transistors as they employ the characteristics of transistors--usually MOS transistors--to either permit or prevent the passage of a signal.
It is well known that switches are widely used in many fields. They are used in all variety of large- and small-scale consumer products, including, but not limited to, automobiles and home electronics. They can be and are used as analog routers, gates, and relays. They are used as digital multiplexers, routers, and gates as well.
As part of continuing developments in the field of semiconductor devices, particularly regarding size and operating speed, there has been a reduction in the amount of power required to operate such devices. Whereas standard operating systems utilize a 5-volt supply for proper operation of MOS and bipolar transistors, reductions of scale have yielded the capability to operate at lower supply levels, including 3-volt and 2-volt systems.
There are limitations, however, in the use of such devices. These limitations are related to fabrication vagaries, and, more significantly, they are related to inherent characteristics. In particular, it is to be noted that there are threshold potential levels that must be overcome in order to activate semiconductor devices. These threshold activation levels are of importance, but not of insurmountable limitation, when the available supply is at least five volts, as is the case in most present systems. The threshold activation for externally-supplied transistors is typically about 0.8 volt. In a system having a high-potential power rail of 5 volts used to supply a logic high or "1" value, and a low-potential power rail of ground, or 0 volt used to supply a logic low or "0" value, for example, a drop in potential on the order of the threshold activation level noted will not cause a loss in system operation or function. That is because a logic high and a logic low signal will be adequately transferred via an NMOS transistor as long as that signal falls within a range of values near the noted rail values.
A number of prior-art transfer gates have been developed for digital and analog applications. However, these devices fail to address problems associated with the transition to operations at the "lower" high-potential levels noted, and they are particularly ineffective when input values go beyond high- and low-potential power rail values. That is, when a transfer gate input potential exceeds the high-potential rail Vcc positively, or it exceeds the low-potential rail GND negatively. One such device that has been in relatively common use is shown in FIG. 1.
A complementary pair of transistors, NMOS transistor M1 and PMOS transistor M2 conduct signals between nodes A and B, where each of those nodes is couplable to an extended circuit. When a control signal OEN (shown in FIG. 1 associated with node A as the input for purposes of illustration only, but which can also be associated with node B as the input) is a logic "high" or "1," transistor M1 is turned on, and as a result of the inversion produced by inverter I1, transistor M2 is also on. In this condition, the two transistors are "on" and the potential at node B is essentially the same as the potential at node A. When OEN is at a logic "low" or "0," both transistors are off and there exists a high impedance for the transfer of any signal between nodes A and B. This is true for all potentials at node A or B that are less than the potential of high-potential power rail Vcc and greater than low-potential power rail GND. However, when either the input or the output node is greater than Vcc or less than GND, the potential associated with the typical logic low at the gate of transistor M1 and a typical logic high at the gate of M2 is insufficient to keep those transistors off. For a potential greater than Vcc, M2 will turn on, for a potential less than GND, M1 will turn on, irrespective of the logic level applied at input OEN. As a result, an overvoltage condition at either the input or the output will cause M1 and M2 to permit a signal to pass through that the OEN deems should be blocked. An undervoltage condition will likewise be passed under the same OEN condition.
For the purpose of this disclosure, the terms "overvoltage" and "undervoltage" mean the potential variations noted that occur under static (DC) conditions as well as dynamic (AC) conditions. For that reason, overvoltage may be used interchangeably with overshoot. Similarly, undervoltage may be used interchangeably with undershoot. Passage of any of those conditions when OEN deems such conditions should be blocked is undesirable.
A device designed to resolve at least one portion of the problems associated with the complementary transfer gate of FIG. 1 is shown in FIG. 2. The device involves removal of PMOS transistor M2, leaving NMOS transistor M1 coupled between nodes A and B, where node A is the input from, or output to, a first extended circuit, and node B is the input from, or output to, a second extended circuit. As before, control node OEN is designed to control enablement of M1. In operation, a logic level high from OEN to the gate of M1 renders M1 on and thereby permits a signal to pass between nodes A and B. A logic level low turns M1 off and blocks the transfer of the signal between A and B. Elimination of transistor M2 resolves the problem when the potential at node A or node B exceeds Vcc because that transistor is not there to be turned on. That does not eliminate the possibility that the transfer gate will turn on when it should be off under conditions of negative voltage exceeding GND.
An alternative and more complex prior transfer gate is shown in FIG. 3. That device includes a series of pass transistors, two of which, M3 and M5, are NMOS transistors, with the intermediate transistor M4 a PMOS transistor. When OEN transmits a logic low or "off" signal, the circuit of FIG. 3 will remain off, even when Vcc and GND are exceeded. However, the effective drain-source resistance R.sub.DS of this device is several hundred ohms, on the order of 500 ohms for an otherwise suitable transfer gate, and is a function of the coupling of the three transistors in series. While that resistance is acceptable in analog devices, it is not so in digital systems where the RC time constant is a critical consideration in the rate of operation of a circuit. Therefore, this transfer gate would not be particularly suitable for digital circuitry that operates at faster and faster rates.
A problem associated with the lower operational potentials previously mentioned remains with the circuit of FIG. 2, its equivalent single-PMOS-transistor transfer gate circuit, and the circuit of FIG. 3. As indicated, degradation in signal level will always occur with the use of semiconductor devices. When Vcc is at 5.0V that is not a problem in that standard transistor-transistor logic (TTL) high-potential levels can be met in spite of such degradation. This degradation, identified as VCC-V.sub.OH, is dependent upon the potential drop or drops that occur as a signal passes through circuit components. For the transistors of the transfer gates of FIGS. 1-3, V.sub.OH is related to the threshold turn-on potential V.sub.TN and the source-bulk potential V.sub.SB, of the transistor or transistors in use by the approximation equation VOH=Vcc-V.sub.TN -.gamma.(V.sub.SB).sup.1/2 where .gamma. is defined as the "body effect factor" of the transistor, and is well known to those skilled in the art. In general, V.sub.OH degradation is approximately 1.4V. When logic high signals associated with 5.0V high-potential rails are on the order of 4.5V-5.5V such degradation is inconsequential in that even a signal at 4.5V-1.4V=3.1V will still be a logic high signal. However, when a 3.3V rail is the voltage source, a degradation of 1.4V may cause a logic high to be interpreted as a logic low. As a result, the prior transfer gates of FIGS. 1-3 cannot be used in relatively low-voltage supplied systems.
Therefore, what is needed is a semiconductor-switching device that is a transfer gate or pass gate suitable for digital and analog operations. What is also needed is such a device that will be operational during all overvoltage/undervoltage conditions, including input/output potentials rising above Vcc and falling below GND. Finally, what is needed is such a transfer gate that can operate in systems using high-potential sources of less than 5.0V.